The present invention relates to a method of fabricating an integrated circuit (IC) chip package and, particularly, to a method of fabricating a multi-chip module using flip-chip bonding technique (interconnection).
As a means for increasing electronic circuit density, a printed-circuit board (PCB) has been used heretofore. A number of IC devices (including LSIs, VLSIs), together with other circuit elements and interconnections between such IC devices and circuit elements, are mounted on a PCB and connections to external circuits are realized by printed wirings on the PCB and/or connectors provided thereon. Each of such IC devices is provided as a single chip package which contains a single IC chip which is usually sealed. Therefore, in order to increase the electronic circuit density on a PCB, it is necessary to increase the wiring density on the PCB so that a larger number of single chip IC devices can be mounted on the PCB. However, since respective IC devices have certain size and the wirings have certain width, it is impossible to increase the circuit density of the PCB beyond a certain limit. Therefore, it is difficult to make a PCB-based device sufficiently compact. Further, in the PCB-based device, it is difficult to dissipate heat generated in respective IC devices. Further, since it is difficult to shorten signal paths within the device, the upper limit of the signal bit rate capable of being processed in that device is low.
As a means for solving these problems, a multi-chip IC package has been proposed, which comprises a ceramic substrate having a multi-layered wiring and a plurality of IC chips mounted thereon and connected to the wiring. In such ceramic substrate-based multi-chip package, the requirements of compactness, improved reliability and shortened signal path can be achieved. However, the problem of heat dissipation can not be fully solved due to the low thermal conductivity of the ceramic substrate. In addition to this, a problem of destruction of IC chips occurs due to differences in thermal expansion between the IC chips and the ceramic substrate.
In view of these difficulties with the ceramic substrate, the use of a silicon substrate rather than the ceramic substrate has been proposed. A silicon wiring substrate has a heat conductivity high enough to solve the problem of heat dissipation and hence the problem of thermal expansion difference. In addition, the use of a silicon substrate is advantageous since the state-of-art techniques for fabricating IC chips which includes lithography technique, inter-layer wiring technique, etc., can be directly used for processing of the silicon circuit substrate. Further, since respective IC chips to be mounted on the silicon circuit substrate in accordance with the multi-chip scheme may be tested after their diffusion processes, the reliability of an assembled multi-chip module becomes high. Further, IC chips to be mounted on the circuit board can be flexibly combined. For example, a combination of MOS IC chips and bipolar IC chips, a combination of MOS IC chips and compound semiconductor IC chips, etc., may be possible. (The above-mentioned prior arts are disclosed in John K. Hagge, "Ultra-Reliable Packaging for Silicon-on-Silicon WSI", IEEE Transactions on Components, Hybrids, and Manufacturing Technology, Vol. 12, No. 2 (Jun. 1989), P. 170 to 179.)
In order to effectively dissipate heat, it is usual to attach a member such as a heat sink intimately onto a surface of a silicon circuit board which is opposite to that on which IC chips are mounted, by means of suitable adhesive. With this construction, heat produced in a plurality of IC chips is transmitted through the silicon circuit board to the heat sink, resulting in insufficient heat dissipation. Particularly, in a multi-chip module having a structure in which a gap is left as it is between the IC chips and the silicon circuit board, the heat dissipation effect is usually insufficient.
A module construction in which a plurality of IC chips are mounted on a silicon circuit board through flip-chip interconnection in face-down configuration and in which the heat sink member is intimately attached to a rear surface of the chip may be optimum for heat dissipation. However, in order to assure the heat dissipation effect, it is necessary that the rear surfaces of the IC chips mounted on the silicon circuit board in a face-down manner are coplanar and the intimate contact of the respective rear surfaces of the IC chips with the heat sink is maintained. That is, it is necessary that the respective IC chips are uniformly fixed on the silicon circuit board. However, when the chips are not uniformly positioned on the substrate but, for example, are tilted relative to the plane of the substrate, a gap may be left between the heat sink men%her and the IC chips, resulting in a degraded thermal conduction therebetween and hence degraded heat dissipation.
The arrangement of the plurality of IC chips fixed on the silicon circuit board with a uniform gap therebetween in thickness direction of the chips is usually realized by using metal bumps provided on either or both of the IC chips and the circuit board for interconnection of the flip-chip. According to the method disclosed in, for example, Japanese Kokai (P) 63-141356 published on Jun. 13, 1988, metal bumps each of Cu or Au whose height is larger than a thickness of a surface insulating film of SiO.sub.2 or SiN formed on an IC chip are formed. On the other hand, the insulating film is formed with holes at positions corresponding to these ]Dumps and solder of Sn, Pb and In, etc., is disposed in each of the holes. The solder is melted when the holes and the bumps are mated with each other, so that the IC chips are fixed to the silicon circuit board. The metal bumps substantially define the gap between the IC chips and the silicon circuit board and the solder contributes to finely regulate the gap.
A technique in which electric connection between IC chips and a silicon circuit board is performed by using not solder but the shrinking effect of photo-polymerizing resin with light illumination has been proposed (cf. R. Harada et al., "Applications of New Assembly Method "Micro Bump Bonding Method"", International Electronic Manufacturing Technology symposium, from P. 47). In this technique, a gap between the IC chip and the silicon circuit board is mainly determined by a sum of heights of metal bumps of Au provided on both the IC chip and the silicon circuit board and the photo-polymerizing resin is used such that the metal bumps are reliably connected electrically when the bumps are mated with each other. As is clear from this construction, it is impossible to finely regulate the gap between the chip and the circuit board after the adhesive resin is photo-polymerized.
The technique disclosed in the above-mentioned Japanese Kokai is advantageous over other prior art techniques in that the gap between the IC chip and the silicon circuit board can be regulated finely by means of the solder disposed in the holes of the surface insulating film. However, there remains the disadvantage that, when the metal bumps of the IC chips are fitted in the holes of the insulating film on the silicon circuit board, a hollow cylindrical gap whose boundary is defined by the molten solder, the side wall of the hole and the bottom portion of the metal bump, is formed in each hole. Air enclosed in these cylindrical gaps may expand by temperature increase after assembling of a multi-chip module, deforming the members defining the space or, in the worst case, destroying a portion of these members. In the conventional technique using solder, the connection and fixing of the IC chips are performed in a single step and, after being fixed, it is difficult to selectively replace a defective IC chip or chips with new one or ones when such defect is detected.